The present invention relates to a synchronizing unit for generating a synchronized pulse sequence from an external signal pulse sequence, with the assistance of an internal work clock sequence.
Synchronizing units have been developed for numerous applications. In general, what is involved is to process an externally supplied signal sequence at the site of a receiver, sYnchronously with an internal work clock sequence, without losing information from the received signal. In a special case, the clock frequency of the external sequence is the same as the frequency of the internal work clock but the two differ from each other in terms of phase.
A special case is when the absolute phase difference between the two clock sequences is not closely limited, and can reach the order of magnitude of a clock cycle, or more. This case frequently occurs in data communications and data processing systems where a central controller provides a central clock, often embedded in the data stream of a message, and peripheral devices need to have their work speed adapted to the frequency of this central clock.
While various means are known for keeping the clock frequency in the individual units constant, or adapting them to the frequency of a reference clock, the phase differences still remain critical. This is due to different transmission times in individual units, and phase delays in transmission paths. For example, in a known data switching network adapted for synchronous and asynchronous modes of operation; means are provided for synchronizing the clocks for synchronous data transmission. A clock generator is arranged at a central location within the data switching network and this clock generator emits clock signals to each subscriber requesting synchronous operations over a separate transmission path, independent of the asynchronous part of the data switching network. These transmission paths have inherent delays and such delays are augmented by individual delay units to a whole multiple of the clock pulse period. In addition, a delay element is inserted in each section of the data switching network which is to be employed by synchronous subscribers, with the delay time of such unit augmenting the delay time of the respective section to a whole multiple of the clock period and shifting, in time, the message at the switching offices and at the subscribers such that it lies in a predetermined phase relationship to the clock.
In such a system, individual compensations must be provided at each receiving station, and such steps are justified only when the overall network is set up for long term operation. In many other applications, however, it is desirable to select and change the locations of peripheral devices without special considerations relating to transit times so as to minimize the difficulty and cost of such installations.
Thus, if individual phase compensations are not suitable for compensating for different transit times over different transmission paths of the individual lengths, then synchronizing units must be provided locally which synchronize transmitted signal sequences, particularly those sequences used in connection with data processing devices.
In this respect there is known a synchronizing circuit having two switching stages using edge-controlled JK flip-flops. Both flip-flops are connected in series, with the outputs of one being connected to the inputs of the other, and they are controlled in common by the same edge of the internal work clock pulses. Signal pulse sequences to be synchronized are supplied to the initialization inputs of the switching stages in a variety of ways through, for example, logic elements. A disadvantage of this type of conventional synchronizing circuit involves the fact that certain limitations must be observed with respect to the duty cycle of the clock, so that the circuits can operate reliably. This is due to the fact that the two serially connected switching stages are each triggered by one and the same clock edge, and the signal status therefor must not change during a critical time period or else an undefined switching state arises. This critical time period lies on both sides of the triggering clock edge, and is dependent upon by the set up and hold times of the bistable switching devices.